Interrupt Question & Answers November 22, 2022 By WatElectronics This article lists 100 Interrupts MCQs for engineering students. All the Interrupts Questions & Answers given below include a hint and a link wherever possible to the relevant topic. This is helpful for users who are preparing for their exams, or interviews, or professionals who would like to brush up on the fundamentals of Interrupts. The interrupts are two types software and hardware interrupt. The RST-restart is the software interrupt and RST 6.5, RST 5.5, TRAP, RST 7.5, and INTR are the hardware interrupts. The hardware interrupts are categorized into two they are maskable and non-maskable interrupts. The non-maskable interrupts can’t be delayed or rejected but the maskable interrupts can be delayed or rejected. The interrupts can be classified into vectored and non-vectored interrupts. The address of the service routine in vectored interrupt is hard-wired and in non-vectored interrupts, the address of the service routine needs to be supplied extremely by the device. The DI interrupt instruction is used to disable the interrupt and the EI interrupt instruction is used to enable the instruction. The DI and EI interrupt instructions both are one-byte instructions. There are two ways to clear TRAP interrupt resetting the microprocessor (external signal) and by giving a high TRAP acknowledgment (internal signal). The RST 6.5, RST 5.5, RST 7.5, and INTR interrupts are maskable whereas the TRAP interrupt is not maskable. The RST 6.5, RST 5.5, TRAP, and RST 7.5 are vectored whereas INTR interrupt is not vectored. The RST 6.5, INTR, and RST 5.5 interrupts are level sensitive whereas the RST 7.5 is positive edge sensitive. 1). Which one of the following is a hardware invoked? Interrupts Traps Both a and b None of the above None Hint 2). Which one of the following are subset of interrupts? Interrupts Traps Both a and b None of the above None Hint 3). Which one of the following are asynchronous? Interrupts Traps Both a and b None of the above None Hint 4). Which one of the following interrupts generated by an input output system? Internal interrupts External interrupts Program generated None of the above None Hint 5). What is the standard form of PIR? Priority Interrupt Register Priority Internal Register Peripheral Interrupt Request None of the above None Hint 6). When interrupt priority enable is zero in global interrupt enable bit the one is equal to _______________? Enables all unmasked interrupts Disables all interrupts Both a and b None of the above None Hint 7). The vector address of an instruction RST0 is ______________________? 0000H 0008H 0010H None of the above None Hint 8). Which one of the following interrupts comes under software interrupt? RST 0 RST 6.5 RST 7.5 None of the above None Hint 9). The trap comes under __________________ type of interrupt? Software Hardware Both a and b None of the above None Hint 10). What is the standard form of ISR? Interrupt Service Runtime Interrupt Single Routine Interrupt Service Routine None of the above None Hint 11). The 8085 has ___________________ number of hardware interrupts? Two Five Six Seven None Hint 12). Which one of the following interrupts can be delayed or rejected? Maskable Non-maskable Both a and b None of the above None Hint 13). The RST 7.5 maskable interrupt is disabled by _____________________? DI instruction System or process or reset After reorganization of an interrupt All of the above None Hint 14). What is the standard form of IRQ? Interrupt Request Lines Integral Request Lines Internal Request Lines None of the above None Hint 15). What is the standard form of IPR? Interrupt Priority Register Internal Priority Register Integral Priority Register None of the above None Hint 16). The TF0 is a ___________________ type of interrupt? Timer 0 overflow interrupt External hardware interrupt Timer1 overflow interrupt None of the above None Hint Read more about Microcontroller 17). What is the address of an external INT 0? 0003h 000Bh 0013h 0023h None Hint 18). The C7 is the machine HEX code of __________________ instruction? RST 0 RST 1 RST 2 RST 3 None Hint 19). The vector address of an instruction RST1 is ______________________? 0000H 0008H 0010H None of the above None Hint 20). What is the standard form of NMI? Non-Maskable Interrupt Non-Maskable Interval Non-Maskable Integral None of the above None Hint 21). The priority of TRAP interrupt of 8085 is __________________? One Two Three Four None Hint 22). The binary equivalent of restart instruction RST 0 is ________________? 1100 0111 1100 1111 1101 0111 1101 1111 None Hint 23). Which one of the following is cannot be masked? CALL INT Both a and b None of the above None Hint 24). Which one of the following interrupts has lowest priority? NMI INTR Single step None of the above None Hint 25). What is the standard form of WDT? Watchdog Timer Range Watchdog Timer Runtime Watchdog Timer Reset None of the above None Hint Interrupt MCQ for Exams 26). Which one of the following is a type of branching instruction? Jump Call Return All of the above None Hint 27). Which one of the following comes under conditional jump instruction? JMP JNC Both a and b None of the above None Hint 28). What is the address of a timer/counter zero? 0003h 000Bh 0013h 0023h None Hint 29). The INT0 is a ___________________ type of interrupt? Timer 0 overflow interrupt External hardware interrupt Timer1 overflow interrupt None of the above None Hint 30). How many types of interrupts are there in MSP430? One Two Four Three None Hint 31). Which one of the following are occurs at a well-defined point in the program? Interrupts Traps Both a and b None of the above None Hint 32). The interrupts are categorized into _______________ types? One Two Four Three None Hint 33). The vector address of an instruction RST2 is ______________________? 0000H 0008H 0010H None of the above None Hint 34). The binary equivalent of restart instruction RST 1 is ________________? 1100 0111 1100 1111 1101 0111 1101 1111 None Hint 35). What is the standard form of PIE? Priority Interrupt Enable Priority Internal Enable Peripheral Interrupt Enable None of the above None Hint 36). The priority of RST 7.5 interrupt of 8085 is __________________? One Two Three Four None Hint 37). Which one of the following is can be masked? CALL INT Both a and b None of the above None Hint 38). What is the address of an external interrupt one? 0003h 000Bh 0013h 0023h None Hint 39). The TF1 is a ___________________ type of interrupt? Timer 1 overflow interrupt External hardware interrupt Timer1 overflow interrupt None of the above None Hint 40). What is the standard form of GIE? Global Interrupt Enable Global Internal Enable Global Integral Enable None of the above None Hint 41). Which one of the following interrupts generated by a user program using INT instruction? Internal interrupts External interrupts Program generated None of the above None Hint 42). The 0018H is a vector address of _____________________ instruction? RST3 RST4 RST5 RST6 None Hint 43). The binary equivalent of restart instruction RST 2 is ________________? 1100 0111 1100 1111 1101 0111 1101 1111 None Hint 44). The priority of RST 6.5 interrupt of 8085 is __________________? One Two Three Four None Hint 45). What is the standard form of BOR? Brown Out Reset Brown Out Runtime Brown Ongoing Reset None of the above None Hint 46). The JC 2050 is an example for __________________ opcode? JC JNC JNZ JPO None Hint 47). Which one of the following instructions uses a 16-bit address similar to long jump instruction? ACALL LCALL Both a and b None of the above None Hint 48). How many forms does 8051 provides for the return instruction? One Two Three Four None Hint 49). The 0020H is a vector address of _____________________ instruction? RST3 RST4 RST5 RST6 None Hint 50). What is the standard form of TAIV? Timer-A Internal Vector Register Timer-A Interrupt Vector Register Timer-A Integral Vector Register None of the above None Hint Interrupt MCQ for Quiz 51). The binary equivalent of restart instruction RST 7 is ________________? 1110 1111 1100 1111 1101 0111 1111 1111 None Hint 52). The JNC 2050 is an example for __________________ opcode? JC JNC JNZ JPO None Hint 53). The TLB miss is an example those caused by an _________________? Instruction External world Both a and b None of the above None Hint 54). The reset button is an example those caused by an _________________? Instruction External world Both a and b None of the above None Hint 55). What is the standard form of PSPIE? Parallel Slave Port Read/write Integral Enable Parallel Slave Port Read/write Internal Enable Parallel Slave Port Read/write Interrupt Enable None of the above None Hint 56). Which one of the following instructions is a two-byte instruction? SJMP LJMP Both a and b None of the above None Hint 57). How many forms does 8051 provides for the call instruction? One Two Three Four None Hint 58). Which one of the following instructions uses an 11-bit address similar to absolute jump instruction? ACALL LCALL Both a and b None of the above None Hint 59). Which one of the following instructions is a three-byte instruction? SJMP LJMP AJMP None of the above None Hint 60). What is the standard form of IVT? Internal Vector Timer Internal Vector Table Internal Vector Register None of the above None Hint 61). Which one of the following interrupts is vectored? INTR RST 5.5 RST 6.5 RST 7.5 None Hint 62). What is the standard form of ICWs? Initialization Command Words Integral Command Words Interrupt Command Words None of the above None Hint 63). The binary equivalent of restart instruction RST 6 is ________________? 1110 1111 1100 1111 1101 0111 1111 0111 None Hint 64). The JP 2050 is an example for __________________ opcode? JC JNC JP JPO None Hint 65). What is the standard form of ADIE? Analog to Digital Converter Integral Enable Analog to Digital Compound Internal Enable Analog to Digital Converter Interrupt Enable None of the above None Hint 66). Which one of the following is not maskable interrupt? INTR RST 5.5 RST 6.5 TRAP None Hint 67). The command words of 8259 A are classified into ________________ types? One Three Two Four None Hint 68). What is the address of a timer/counter one? 0003h 000Bh 0013h 001Bh None Hint 69). The 0028H is a vector address of _____________________ instruction? RST3 RST4 RST5 RST6 None Hint 70). Which one of the following is a software invoked? Interrupts Traps Both a and b None of the above None Hint 71). The call instructions are categorized into __________________ types? Two Three Four Five None Hint 72). The initialization of stack pointer is not mandatory in __________________ instruction? JUMP CALL Both a and b None of the above None Hint 73). In which one of the following instruction the value of stack pointer does not change? JUMP CALL Both a and b None of the above None Hint 74). In ______________ instruction, three machine cycles are required to execute the instruction? JUMP CALL Both a and b None of the above None Hint 75). What is the standard form of RCIE? Receive Interrupt Enable Receive Internal Enable Receive Integral Enable None of the above None Hint Interrupt MCQ for Interviews 76). The binary equivalent of restart instruction RST 5 is ________________? 1110 1111 1100 1111 1101 0111 1101 1111 None Hint 77). How many machine cycles are required to execute the call instruction? One Two Three Four None Hint 78). In which one of the following instruction 10 T states are required to execute the instruction? JUMP CALL Both a and b None of the above None Hint 79). The RC is an example for _______________ op-code? RNC RET RC None Hint 80). Which one of the following is a single emitted by a hardware device? Interrupts Traps Both a and b None of the above None Hint 81). Which one of the following instructions is used to enable the interrupt? DI instructions EI instructions Both a and b None of the above None Hint 82). The binary equivalent of restart instruction RST 4 is ________________? 1100 0111 1100 1111 1101 0111 1101 1111 None Hint 83). In which one of the following instruction the initialization of SP is mandatory? JUMP CALL Both a and b None of the above None Hint 84). The priority of INTR interrupt of 8085 is __________________? One Two Three Five None Hint 85). What is the standard form of TXIE? Transmit Interrupt Enable Timer Internal Enable Transformer Integral Enable None of the above None Hint 86). Which one of the following is a BIOS interrupt? INT 16h INT 21h Both a and b None of the above None Hint 87). What is the standard form of SFNM? Serial Fully Nested Mode Special Fully Nested Mode Single Fully Nested Mode None of the above None Hint 88). What is the address of a serial port? 0003h 000Bh 0013h 0023h None Hint 89). The 0030H is a vector address of _____________________ instruction? RST3 RST4 RST5 RST6 None Hint 90). Which one of the following is a single emitted by a user program? Interrupts Traps Both a and b None of the above None Hint 91). Which one of the following interrupts comes under hardware interrupt? RST0 RST1 RST7.5 None of the above None Hint 92). The priority of RST 5.5 interrupt of 8085 is __________________? One Two Three Four None Hint 93). The binary equivalent of restart instruction RST 3 is ________________? 1100 0111 1100 1111 1101 0111 1101 1111 None Hint 94). What is the standard form of OCWs? Operation Command Words Operation Control Words Operation Command Wide None of the above None Hint 95). What is the standard form of TMR1IE? Timer1 Overflow Interrupt Enable Timer1 Overflow Internal Enable Timer1 Overflow Integral Enable None of the above None Hint 96). The RST 6.5 and RST 5.5 maskable interrupts are disabled by __________________? DI, system instruction System or process or reset After reorganization of an interrupt All of the above None Hint 97). Which one of the following instructions is used to disable the interrupt? DI instructions EI instructions Both a and b None of the above None Hint 98). Which one of the following interrupts cannot be delayed or rejected? Maskable Non-maskable Both a and b None of the above None Hint 99). The 0038H is a vector address of _____________________ instruction? RST3 RST4 RST5 RST7 None Hint 100). Which one of the following are superset of traps? Interrupts Traps Both a and b None of the above None Hint Please fill in the comment box below. Time's up
