Direct Memory Access Question & Answers December 13, 2021 By WatElectronics This Article lists 100+ Direct Memory Access MCQs for engineering students. All the Direct Memory Access Questions & Answers given below includes solution and link wherever possible to the relevant topic. The term DMA stands for direct memory access and it is a feature in computer networks. This feature permits particular hardware systems to allow the memory of the main system like RAM separately from the CPU. Many systems use direct memory access like graphics cards, sound cards, disk drive controllers, network cards, etc. In multi-core processors, direct memory access can also be used for intra chip data transfer. Computers including DMA channels transfer data from one device to other with very little CPU overhead as compared to computers with no DMA. Likewise, a processing element in a multi-core computer can transmit data to its local memory without using its processor time, allowing calculation & data transfer to continue in parallel. 1). Access to the I/O devices through the peripheral bus is? Slower than the system bus. Faster than the system bus. Similar to the system bus. None of the above None Hint 2). DMA transfers data between------- Memory and processor. Processor and I/O devices. I/O devices and memory. All of the above. None Hint 3). DMA stands for----? Digital Memory Access. Direct Memory arbitration. Direct Memory Access. Digital Memory Accessibility None Hint 4). For transfer of data, devices inform the DMA through------? Bus request signal. DRQ. HLDA DAK None Hint 5). DMA acts as------ to the CPU for data transfer. Master Slave. Both a and b. None of the above None Hint 6). -------- programs the DMA controller? System memory. I/O peripherals. CPU. Internal registers None Hint 7). DMA controller is connected to--------- Processor. System bus. Peripheral bus. I/O devices None Hint 8). DMA controllers vary depending on-------? Type of DMA transfer. The number of DMA channels. The speed of DMA. Both a and b. None Hint 9). The number of I/O devices controlled by DMA depends on---? Size of the processor. Speed of the processor. Number of channels of the DMA. Number of DMA registers None Hint 10). Fastest DMA transfer type is------ Flyby DMA transfers. Fetch and deposit transfer. Demand transfer. None of the above. None Hint 11). Fetch and deposit transfer is also known as---? Dual-cycle transfer. Dual-address transfer. Flow-through transfer. All of the above None Hint 12). The---------transfer is more efficient for interfacing devices with different data bus sizes? Fetch and deposit transfer. Flyby transfer. Both a and b. None of the above None Hint 13). Slowest transfer mode of DMA is----- Single transfer mode. Block transfer mode. Demand transfer mode. None of the above None Hint 14). DMA controller performs multiple DMA transfers in -----mode? Single mode. Block mode. Demand mode. Both b and c None Hint 15). -------determines the number of DMA transfers remaining? Base register. Current count registers. CPU. None of the above None Hint 16). ---------- is useful for performing double buffered data acquisition. Auto-initialization. Buffer chaining. Cycle stealing. None of the above None Hint 17). While making network interfaces transfers, DMA makes use of--------------? Base register Count register. Input buffer storage. All of the above. None Hint 18). When there are no pending valid DMA requests 82C37A enters into------? State I State 0 State 1 State 4 None Hint 19). The first four states of 82C37A are used for-------? Read from I/O. Read from memory. Write to I/O. Write to memory None Hint 20). The DMA controller is programmed using ------------ Command and Mode registers. Address register. Word count register. All of the above. None Hint 21). DREQ is a------------signal. Hardware signal. Software command. Either a or b. None of the above. None Hint 22). The controller stops transferring when-----? Word count register underflows. External EOP is applied. Either a or b. None of the above. None Hint 23). After programming, until the DMA request occurs, the controller will be in the----------state? Ideal. Active. Wait state. Working state None Hint 24). 8257 DMA controller is a------? 2 channel DMA. 3 channel DMA. 4 channel DMA. 8 channel DMA None Hint 25). In 8257 DMA the address of the first memory location to be accessed is loaded in------? Terminal count register DMA address register. Buffer register. None of the above None Hint Direct Memory Access Question & Answers for Interviews 26). For each channel 8257 DMA controller has two------registers? 14 bit 16 bit 20 bit 32 bit None Hint Please refer to this link for Shift Registers 27). Type of operation of the channel in 8257 is indicated by-------bits of terminal count register? Least significant 2 bits. Most significant 2 bits. Least significant 4 bits. Most significant 4 bits None Hint 28). DMA transfers can cause-----? High processor loads. More memory usage. Decrease in speed of processor. Cache coherence None Hint 29). To initiate the transfers the processor programs the DMA by sending-----? Starting Address. Number of words in a block. Direction of transfer All of the above. None Hint 30). While accessing the bus DMA controller is given -----? Higher priority than processor. Lower priority than processor. Equal priority to the processor. First come first serve bases None Hint 31). ---------has higher reliability. Centralized bus arbitration. Distributed bus arbitration. Single master. Both a and b None Hint 32). In-------mode, DMA gives control of buses to CPU after transfer of every byte of data? Burst mode. Cycle stealing mode. Transparent mode. Block mode None Hint 33). Modes of operation in DMA includes….? 2 3 4 5 None Hint 34). Which of the following offers an efficient technique to transfer the information from a device to memory? ROM DMA Bus Serial Port None Hint 35). Which of the following doesn’t contain a DMA? Polling Register Timer Memory None Hint 36). Which of the device contains buffer filling with low range? Register Peripheral Timer DMA None Hint 37). The DMA controllers depending on the capacity of addressing are….? 2 3 4 5 None Hint 38). In 1D type DMA, how many address registers are there? 1 3 4 5 None Hint 39). A data bus is used to transfer the information from ……to destination? CPU Memory Register DMA None Hint 40). The bus request from the CPU can be done by using…..? Data bus Requester Register Address bus None Hint 41). The signal used to recognize the error within DMA is….? HOLD Interrupt Digital HLDA None Hint 42). Which of the following signal allows the DMA to choose the peripheral? HOLD Local peripheral control HLDA Address bus None Hint 43). A buffer used by an address mode within DMA for data holding temperorily? 1D 2D 3D Dual address model None Hint 44). An address stride can be provided by…..model? 1D 2D Singal address Dual address None Hint 45). The data transfer in DMA can be controlled through….? I/O devices Microprocessor BUS CPU None Hint 46). Cycle stealing method is used in…? Data transfer based on Interrupt Data transfer based on Polled mode BUS DMA based data transfer None Hint 47). For which of the following, access time is very faster? ROM SRAM RAM ERAM None Hint 48). The data transfer within a DMA is ….? From CPU to memory From I/O to RAM From memory to I/O From memory - memory None Hint 49). The DMA transfer can be done started through…? Operating system Processor Memory I/O devices None Hint 50). The data transfer mode among the memory & I/O devices is called…? DMA Pipelining Fetching Black mode None Hint Direct Memory Access Question & Answers for Exams 51). The performance of DMA transfer can be done through ……? Data controller Over looker Device interface DMA controller None Hint 52). In direct memory access transfers, the necessary addresses & signals are provided by the…? DMA controller Over looker Data controller Device interface None Hint 53). The DMA controller includes….registers? 2 3 4 5 None Hint 54). Which of the following bus is used to connect the controller? System bus Serial bus Parallel bus External bus None Hint 55). The method where the DMA steals the processor’s access cycles to manage is known as…? Memory Con Fast conning Memory stealing Cycle stealing None Hint 56). The method which is used by the controller to provide complete access for main memory is? Memory Con Burst memory Cycle stealing Fast conning None Hint 57). The DMA controller registers are….? 8 bits 16 bits 32 bits 64 bits None Hint 58). To reduce the clash on the BUS possession, we use ______? BUS arbitrators Optimizers RAM BUS None Hint 59). Which of the following technique avoids the CPU for particular data transfer types? DMA Interrupts Optimizers Data controller None Hint 60). The technique used for the long distance communication is? Serial Serial parallel Parallel Parallel serial None Hint 61). Cycle stealing is used for data transfer based on…? DMA Polling mode CLK cycle Interrupt None Hint 62). Which of the following device assists DMA transfer? DMA controller Bus arbitizers CLK cycle Optimizers None Hint 63). How many types of DMA transfer? 2 3 4 5 None Hint 64). The DMA channels numbered in old computers are…? 2 3 4 5 None Hint 65). The 16-bit industry standard architecture introduced ……bus? System bus. Address bus Peripheral bus. Expansion bus None Hint 66). The industry standard architecture or ISA is a…? Computer bus. Processor. Memory. Expansion bus. None Hint 67). The data transferred by each DMA per second is? 2 MB 3 MB 4 MB 5 MB None Hint 68. The system resources are classified into …types? 2 4 6 8 None Hint 69). Types of DMA device? 2 3 5 7 None Hint 70). Host platform DMA are classified into…types? 2 3 5 7 None Hint 71). Components in the DMA software are…types? 2 3 4 6 None Hint 72). The most complex microcontrollers uses ……controller? DMA Programmable Interrupt Controller Keyboard controller NIC None Hint 73). How many DMA controllers are there in high density devices? 2 3 4 5 None Hint 74). Which of the following is used to transfer the data from memory to memory, peripheral to peripheral & peripheral to memory? DMA NIC CPU Keyboard controller None Hint 75). DMA channels assigned one of …. Priority levels? 2 3 4 5 None Hint Direct Memory Access Question & Answers for Quiz 76). DMA channel is configured to transmit data into the …. ? Circular buffer CPU Memory Processor None Hint 77). Which of the following is a perfect solution for data stream? DMA Processor CPU Memory None Hint 78). Which of the following accesses only … for transferring actual data? DMA BUS CPU Memory None Hint 79). DMA uses …. Bus cycles to transfer single word between memories? 5 AHB 3 AHB 4 AHB 2 AHB None Hint 80). Every channel in DMA programming can be controlled through? Memory Registers I/O devices Bus None Hint 81). Registers used in DMA controller programming includes…? 2 3 4 5 None Hint 82). What is DTFR? DMA Trigger Factor Register Data Transfer Factor Register Digital Transfer Frequency Register Data Trigger Frequency Register None Hint 83). What is DMAC? Direct Memory Access Controller Direct Multiple Access Controller Direct Memory Access Controller Data Memory Access Controller None Hint 84). In DMA mode, how the data transfer can be done…? Indirectly Indirectly Both None of the above None Hint 85). In 8257 DMA, very four channels include? Set of 2 8-bit registers Set of 2 16-bit registers Single 8-bit register Single 6-bit register None Hint 86). Which of the following pin is used to disable all the DMA channels through removing the mode registers is? CLEAR MARK RESET READY None Hint 87). Which of the following pin is used to write data throughout DMA write operation? AEN MEMR LOW MEMW None Hint 88). The pin that is used to strobe the maximum memory address byte can be generated through the DMA into the latch can be done by? MEMR AEN ADSTB TC None Hint 89). The DMA controller at a time access how many channels? 0 1 2 4 None Hint 90). DMA controller IC includes….pins? 25 30 40 45 None Hint 91). 8237 DMA IC includes …I/O channels? 2 3 4 5 None Hint 92). The main blocks in the 8237A are? 2 3 4 5 None Hint 93). Which of the following block is used to decode the microprocessor commands given to the DMA? Program command control Timing control Priority encoder Priority decoder None Hint Please refer to this link to know more about Microprocessor 94). 8237A operates in … cycles? 2 3 4 5 None Hint 95). In8237A, each cycle includes…states? 2 4 5 7 None Hint 96). Every channel in 8257 IC includes ….registers? 2 4 5 7 None Hint 97). The overload work on the CPU can be decreased by…? DMA Processor RAM Controller None Hint 98). Which of the following problem occurs while DMA transfers the data? Memory loss Cache coherence Low data transfer speed Increases the system price None Hint 99). In which of the following IC includes two 16-bit registers 8257 LM314 IC741 LM808 None Hint 100). Which of the mode is fastest in DMA Burst or block transfer DMA Cascade transfer Demand transfer Black transfer None Hint Time's up
